From f48ad5b29d6f291b4f3679ff5fb7b5beae10d6fa Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Thu, 2 Jun 2016 13:38:30 +0100 Subject: arm: Correctly check FP/SIMD access permission in aarch32 The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1 and higher are all 32-bit. This breaks interprocessing since an aarch64 EL1 uses different enable/disable bits. This change updates the permission checks to according to what is prescribed by the ARM ARM. Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88 Signed-off-by: Andreas Sandberg Reviewed-by: Mitch Hayenga Reviewed-by: Nathanael Premillieu --- src/arch/arm/isa/templates/neon.isa | 27 ++++++--------------------- 1 file changed, 6 insertions(+), 21 deletions(-) (limited to 'src/arch/arm/isa/templates/neon.isa') diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa index 45df741e7..9e9b79957 100644 --- a/src/arch/arm/isa/templates/neon.isa +++ b/src/arch/arm/isa/templates/neon.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2012 ARM Limited +// Copyright (c) 2010-2012, 2016 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -40,26 +40,11 @@ let {{ simdEnabledCheckCode = ''' { - uint32_t issEnCheck; - bool trapEnCheck; - uint32_t seq; - if (!vfpNeonEnabled(seq, Hcptr, Nsacr, Cpacr, Cpsr, issEnCheck, - trapEnCheck, xc->tcBase(), Fpexc, true)) - {return disabledFault();} - if (trapEnCheck) { - CPSR cpsrEnCheck = Cpsr; - if (cpsrEnCheck.mode == MODE_HYP) { - return std::make_shared( - machInst, issEnCheck, - EC_TRAPPED_HCPTR); - } else { - if (!inSecureState(Scr, Cpsr)) { - return std::make_shared( - machInst, issEnCheck, - EC_TRAPPED_HCPTR); - } - } - } + Fault fault = checkAdvSIMDOrFPEnabled32(xc->tcBase(), + Cpsr, Cpacr, Nsacr, Fpexc, + true, true); + if (fault != NoFault) + return fault; } ''' }}; -- cgit v1.2.3