From 0f9a3671b6d12f887501bc80ca50bb23c383686d Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Tue, 18 Jan 2011 16:30:02 -0600
Subject: ARM: Add support for moving predicated false dest operands from
 sources.

---
 src/arch/arm/isa/templates/pred.isa | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'src/arch/arm/isa/templates/pred.isa')

diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index b5bdbc40e..c9e7b1803 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -71,6 +71,11 @@ def template DataImmConstructor {{
                          _dest, _op1, _imm, _rotC)
     {
         %(constructor)s;
+        if (!(condCode == COND_AL || condCode == COND_UC)) {
+            for (int x = 0; x < _numDestRegs; x++) {
+                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+            }
+        }
     }
 }};
 
@@ -97,6 +102,11 @@ def template DataRegConstructor {{
                          _dest, _op1, _op2, _shiftAmt, _shiftType)
     {
         %(constructor)s;
+        if (!(condCode == COND_AL || condCode == COND_UC)) {
+            for (int x = 0; x < _numDestRegs; x++) {
+                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+            }
+        }
     }
 }};
 
@@ -123,6 +133,11 @@ def template DataRegRegConstructor {{
                          _dest, _op1, _op2, _shift, _shiftType)
     {
         %(constructor)s;
+        if (!(condCode == COND_AL || condCode == COND_UC)) {
+            for (int x = 0; x < _numDestRegs; x++) {
+                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+            }
+        }
     }
 }};
 
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