From f4fd12d49e9a4aea3ab3b538301b5fd0f657137b Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Mon, 4 Mar 2013 23:33:47 -0500
Subject: ARM: fix some cases where instructions that write to fp reg 15 are
 accidently branches.

---
 src/arch/arm/isa/templates/pred.isa | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/arch/arm/isa/templates/pred.isa')

diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 918029cc2..42f515a3c 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -77,7 +77,7 @@ def template DataImmConstructor {{
             }
         }
 
-        if (%(is_branch)s){
+        if (%(is_branch)s && !isFloating()){
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (condCode == COND_AL || condCode == COND_UC)
@@ -117,7 +117,7 @@ def template DataRegConstructor {{
             }
         }
 
-        if (%(is_branch)s){
+        if (%(is_branch)s && !isFloating()){
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (condCode == COND_AL || condCode == COND_UC)
-- 
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