From bd0c2d5b0bf512aa5c172fe5676e151913e5e97d Mon Sep 17 00:00:00 2001
From: Mitch Hayenga <mitch.hayenga@arm.com>
Date: Thu, 13 Oct 2016 19:22:10 +0100
Subject: isa,arm: Add missing AArch32 FP instructions

This commit adds missing non-predicated, scalar floating point
instructions.  Specifically VRINT* floating point integer rounding
instructions and VSEL* floating point conditional selects.

Change-Id: I23cbd1389f151389ac8beb28a7d18d5f93d000e7
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
---
 src/arch/arm/isa/templates/vfp.isa | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

(limited to 'src/arch/arm/isa/templates')

diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa
index 1c945cddc..d94f4652a 100644
--- a/src/arch/arm/isa/templates/vfp.isa
+++ b/src/arch/arm/isa/templates/vfp.isa
@@ -210,3 +210,30 @@ def template FpRegRegRegOpConstructor {{
         }
     }
 }};
+
+def template FpRegRegRegCondOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+  public:
+    // Constructor
+    %(class_name)s(ExtMachInst machInst,
+                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+                  ConditionCode _cond,
+                   VfpMicroMode mode = VfpNotAMicroop);
+    %(BasicExecDeclare)s
+};
+}};
+
+def template FpRegRegRegCondOpConstructor {{
+    %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          IntRegIndex _dest,
+                                          IntRegIndex _op1,
+                                          IntRegIndex _op2,
+                                          ConditionCode _cond,
+                                          VfpMicroMode mode)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+                         _dest, _op1, _op2, _cond, mode)
+    {
+        %(constructor)s;
+    }
+}};
-- 
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