From be096f91b94ded36f43dd7d547a5671f99a264b1 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Mon, 4 Apr 2011 11:42:27 -0500
Subject: ARM: Tag appropriate instructions as IsReturn

---
 src/arch/arm/isa/templates/branch.isa |  4 ++++
 src/arch/arm/isa/templates/mem.isa    | 18 ++++++++++++++++++
 src/arch/arm/isa/templates/pred.isa   | 13 +++++++++++++
 3 files changed, 35 insertions(+)

(limited to 'src/arch/arm/isa/templates')

diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index 6abf76963..3a8fbb363 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -120,6 +120,8 @@ def template BranchRegConstructor {{
         } else {
             flags[IsUncondControl] = true;
         }
+        if (%(is_ras_pop)s)
+            flags[IsReturn] = true;
     }
 }};
 
@@ -150,6 +152,8 @@ def template BranchRegCondConstructor {{
         } else {
             flags[IsUncondControl] = true;
         }
+        if (%(is_ras_pop)s)
+            flags[IsReturn] = true;
     }
 }};
 
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index dcfd47ace..f26ee55e8 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -1188,7 +1188,9 @@ def template LoadRegConstructor {{
                  (IntRegIndex)_index)
     {
         %(constructor)s;
+        bool conditional = false;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
+            conditional = true;
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
@@ -1204,6 +1206,12 @@ def template LoadRegConstructor {{
             uops[1] = new %(wb_decl)s;
             uops[1]->setDelayedCommit();
             uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
+            uops[2]->setFlag(StaticInst::IsControl);
+            uops[2]->setFlag(StaticInst::IsIndirectControl);
+            if (conditional)
+                uops[2]->setFlag(StaticInst::IsCondControl);
+            else
+                uops[2]->setFlag(StaticInst::IsUncondControl);
             uops[2]->setLastMicroop();
         } else if(_dest == _index) {
             IntRegIndex wbIndexReg = INTREG_UREG0;
@@ -1234,7 +1242,9 @@ def template LoadImmConstructor {{
                  (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
     {
         %(constructor)s;
+        bool conditional = false;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
+            conditional = true;
             for (int x = 0; x < _numDestRegs; x++) {
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
@@ -1249,6 +1259,14 @@ def template LoadImmConstructor {{
             uops[1] = new %(wb_decl)s;
             uops[1]->setDelayedCommit();
             uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
+            uops[2]->setFlag(StaticInst::IsControl);
+            uops[2]->setFlag(StaticInst::IsIndirectControl);
+            if (conditional)
+                uops[2]->setFlag(StaticInst::IsCondControl);
+            else
+                uops[2]->setFlag(StaticInst::IsUncondControl);
+            if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s)
+                uops[2]->setFlag(StaticInst::IsReturn);
             uops[2]->setLastMicroop();
         } else {
             uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 2a4bd9dab..95c7c8e1b 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -107,6 +107,19 @@ def template DataRegConstructor {{
                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
             }
         }
+
+        if (%(is_branch)s){
+            flags[IsControl] = true;
+            flags[IsIndirectControl] = true;
+            if (condCode == COND_AL || condCode == COND_UC)
+                flags[IsCondControl] = true;
+            else
+                flags[IsUncondControl] = true;
+        }
+
+        if (%(is_ras_pop)s) {
+            flags[IsReturn] = true;
+        }
     }
 }};
 
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