From 04300e33d49e5697565eb39956849a18ad74ea45 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:58:01 -0500 Subject: ARM: Remove the special naming for the new memory instructions. These are the only memory instructions now. --- src/arch/arm/isa/insts/ldr.isa | 16 ++++++++-------- src/arch/arm/isa/insts/mem.isa | 10 +++++----- src/arch/arm/isa/insts/str.isa | 16 ++++++++-------- 3 files changed, 21 insertions(+), 21 deletions(-) (limited to 'src/arch/arm/isa') diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index 259a46fd9..86cb76383 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -64,10 +64,10 @@ let {{ (newHeader, newDecoder, - newExec) = newLoadStoreBase(name, Name, imm, - eaCode, accCode, - memFlags, instFlags, - base, execTemplateBase = 'Load') + newExec) = loadStoreBase(name, Name, imm, + eaCode, accCode, + memFlags, instFlags, + base, execTemplateBase = 'Load') header_output += newHeader decoder_output += newDecoder @@ -93,7 +93,7 @@ let {{ accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size) if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewImm", post, writeback) + base = buildMemBase("MemoryImm", post, writeback) emitLoad(name, Name, True, eaCode, accCode, [], [], base) @@ -118,7 +118,7 @@ let {{ accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size) if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewReg", post, writeback) + base = buildMemBase("MemoryReg", post, writeback) emitLoad(name, Name, False, eaCode, accCode, [], [], base) @@ -143,7 +143,7 @@ let {{ ''' if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewImm", post, writeback) + base = buildMemBase("MemoryImm", post, writeback) emitLoad(name, Name, True, eaCode, accCode, [], [], base) @@ -169,7 +169,7 @@ let {{ ''' if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewReg", post, writeback) + base = buildMemBase("MemoryReg", post, writeback) emitLoad(name, Name, False, eaCode, accCode, [], [], base) diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa index 698f95adb..a7aa0b2ed 100644 --- a/src/arch/arm/isa/insts/mem.isa +++ b/src/arch/arm/isa/insts/mem.isa @@ -38,8 +38,8 @@ // Authors: Gabe Black let {{ - def newLoadStoreBase(name, Name, imm, eaCode, accCode, memFlags, - instFlags, base = 'MemoryNew', execTemplateBase = ''): + def loadStoreBase(name, Name, imm, eaCode, accCode, memFlags, + instFlags, base = 'Memory', execTemplateBase = ''): # Make sure flags are in lists (convert to lists if not). memFlags = makeList(memFlags) instFlags = makeList(instFlags) @@ -131,11 +131,11 @@ let {{ def buildMemBase(base, post, writeback): if post and writeback: - base = "MemoryNewPostIndex<%s>" % base + base = "MemoryPostIndex<%s>" % base elif not post and writeback: - base = "MemoryNewPreIndex<%s>" % base + base = "MemoryPreIndex<%s>" % base elif not post and not writeback: - base = "MemoryNewOffset<%s>" % base + base = "MemoryOffset<%s>" % base else: raise Exception, "Illegal combination of post and writeback" return base diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index e72ca6e41..3349ba029 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -66,10 +66,10 @@ let {{ (newHeader, newDecoder, - newExec) = newLoadStoreBase(name, Name, imm, - eaCode, accCode, - memFlags, instFlags, - base, execTemplateBase = 'Store') + newExec) = loadStoreBase(name, Name, imm, + eaCode, accCode, + memFlags, instFlags, + base, execTemplateBase = 'Store') header_output += newHeader decoder_output += newDecoder @@ -95,7 +95,7 @@ let {{ accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewImm", post, writeback) + base = buildMemBase("MemoryImm", post, writeback) emitStore(name, Name, True, eaCode, accCode, [], [], base) @@ -120,7 +120,7 @@ let {{ accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewReg", post, writeback) + base = buildMemBase("MemoryReg", post, writeback) emitStore(name, Name, False, eaCode, accCode, [], [], base) @@ -142,7 +142,7 @@ let {{ accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);' if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewImm", post, writeback) + base = buildMemBase("MemoryImm", post, writeback) emitStore(name, Name, True, eaCode, accCode, [], [], base) @@ -165,7 +165,7 @@ let {{ accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);' if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryNewReg", post, writeback) + base = buildMemBase("MemoryReg", post, writeback) emitStore(name, Name, False, eaCode, accCode, [], [], base) -- cgit v1.2.3