From 8af1eeec6f28d9722802bf1588c911711db07ddd Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Mon, 4 Apr 2011 11:42:29 -0500
Subject: ARM: Use CPU local lock before sending load to mem system.

This change uses the locked_mem.hh header to handle implementing CLREX. It
simplifies the current implementation greatly.
---
 src/arch/arm/isa/insts/misc.isa     |  8 ++----
 src/arch/arm/isa/operands.isa       |  1 +
 src/arch/arm/isa/templates/misc.isa | 51 -------------------------------------
 3 files changed, 3 insertions(+), 57 deletions(-)

(limited to 'src/arch/arm/isa')

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 35df88c81..7333faef0 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -680,18 +680,14 @@ let {{
     exec_output += PredOpExecute.subst(setendIop)
 
     clrexCode = '''
-        unsigned memAccessFlags = Request::CLEAR_LL |
-            ArmISA::TLB::AlignWord | Request::LLSC;
-        fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
+        LLSCLock = 0;
     '''
     clrexIop = InstObjParams("clrex", "Clrex","PredOp",
                              { "code": clrexCode,
                                "predicate_test": predicateTest },[])
-    header_output += ClrexDeclare.subst(clrexIop)
+    header_output += BasicDeclare.subst(clrexIop)
     decoder_output += BasicConstructor.subst(clrexIop)
     exec_output += PredOpExecute.subst(clrexIop)
-    exec_output += ClrexInitiateAcc.subst(clrexIop)
-    exec_output += ClrexCompleteAcc.subst(clrexIop)
 
     isbCode = '''
         fault = new FlushPipe;
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 49a860213..b497564b7 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -227,6 +227,7 @@ def operands {{
     'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
     'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
     'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
+    'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
 
     #Register fields for microops
     'URa' : intReg('ura'),
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 694dc46da..212897aa0 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -402,54 +402,3 @@ def template RegImmRegShiftOpConstructor {{
     }
 }};
 
-def template ClrexDeclare {{
-    /**
-     * Static instruction class for "%(mnemonic)s".
-     */
-    class %(class_name)s : public %(base_class)s
-    {
-      public:
-
-        /// Constructor.
-        %(class_name)s(ExtMachInst machInst);
-
-        %(BasicExecDeclare)s
-
-        %(InitiateAccDeclare)s
-
-        %(CompleteAccDeclare)s
-    };
-}};
-
-def template ClrexInitiateAcc {{
-    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
-                                      Trace::InstRecord *traceData) const
-    {
-        Fault fault = NoFault;
-        %(op_decl)s;
-        %(op_rd)s;
-
-        if (%(predicate_test)s)
-        {
-            if (fault == NoFault) {
-                unsigned memAccessFlags = Request::CLEAR_LL |
-                    ArmISA::TLB::AlignWord | Request::LLSC;
-                fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
-            }
-        } else {
-            xc->setPredicate(false);
-        }
-
-        return fault;
-    }
-}};
-
-def template ClrexCompleteAcc {{
-    Fault %(class_name)s::completeAcc(PacketPtr pkt,
-                                      %(CPU_exec_context)s *xc,
-                                      Trace::InstRecord *traceData) const
-    {
-        return NoFault;
-    }
-}};
-
-- 
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