From 982a7d4f13e8919cd50dccc29d001f1e98fc2fbb Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 29 Aug 2019 09:26:35 +0100 Subject: arch-arm: Add explicit AArch64 MiscReg banking Change-Id: I89836d14491a51b1573f45c8012e3ad12b107d24 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20623 Maintainer: Andreas Sandberg Tested-by: kokoro --- src/arch/arm/isa/insts/data64.isa | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'src/arch/arm/isa') diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index a2ffb9f5a..f5be4763a 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -331,16 +331,18 @@ let {{ ''' msr_check_code = ''' + auto pre_flat = (MiscRegIndex)snsBankedIndex64(dest, xc->tcBase()); MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()-> - flattenRegId(RegId(MiscRegClass, dest)).index(); + flattenRegId(RegId(MiscRegClass, pre_flat)).index(); CPSR cpsr = Cpsr; ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; %s ''' % (msrMrs64EnabledCheckCode % ('Write'),) mrs_check_code = ''' + auto pre_flat = (MiscRegIndex)snsBankedIndex64(op1, xc->tcBase()); MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()-> - flattenRegId(RegId(MiscRegClass, op1)).index(); + flattenRegId(RegId(MiscRegClass, pre_flat)).index(); CPSR cpsr = Cpsr; ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; %s @@ -509,8 +511,10 @@ let {{ def buildMsrImmInst(mnem, inst_name, code): global header_output, decoder_output, exec_output msrImmPermission = ''' - auto misc_index = (MiscRegIndex) xc->tcBase()->flattenRegId( - RegId(MiscRegClass, dest)).index(); + auto pre_flat = + (MiscRegIndex)snsBankedIndex64(dest, xc->tcBase()); + MiscRegIndex misc_index = (MiscRegIndex) xc->tcBase()-> + flattenRegId(RegId(MiscRegClass, pre_flat)).index(); if (!miscRegInfo[misc_index][MISCREG_IMPLEMENTED]) { return std::make_shared( -- cgit v1.2.3