From aade63a8fec1bf3e302ccce630c718a79d7b3907 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:11 -0500
Subject: ARM: Implement the VMRS instruction.

---
 src/arch/arm/isa/insts/fp.isa | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'src/arch/arm/isa')

diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 7d0fbed85..0beb167dd 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -49,4 +49,11 @@ let {{
     header_output += RegRegOpDeclare.subst(vmsrIop);
     decoder_output += RegRegOpConstructor.subst(vmsrIop);
     exec_output += PredOpExecute.subst(vmsrIop);
+
+    vmrsIop = InstObjParams("vmrs", "Vmrs", "RegRegOp",
+                            { "code": "Dest = MiscOp1;",
+                              "predicate_test": predicateTest }, [])
+    header_output += RegRegOpDeclare.subst(vmrsIop);
+    decoder_output += RegRegOpConstructor.subst(vmrsIop);
+    exec_output += PredOpExecute.subst(vmrsIop);
 }};
-- 
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