From d6736384b2bb280ec12d472cac6eb25a70b4af60 Mon Sep 17 00:00:00 2001 From: Gene Wu Date: Mon, 23 Aug 2010 11:18:41 -0500 Subject: MEM: Make CLREX a first class request operation and clear locks in caches when it in received --- src/arch/arm/isa/insts/misc.isa | 2 +- src/arch/arm/isa/templates/misc.isa | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/isa') diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 2228a0f24..33197eaec 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -669,7 +669,7 @@ let {{ exec_output += PredOpExecute.subst(setendIop) clrexCode = ''' - unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC; + unsigned memAccessFlags = Request::CLREX|3|Request::LLSC; fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); ''' clrexIop = InstObjParams("clrex", "Clrex","PredOp", diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index d2224dc6d..46af3f5b1 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -367,7 +367,7 @@ def template ClrexInitiateAcc {{ if (%(predicate_test)s) { if (fault == NoFault) { - unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC; + unsigned memAccessFlags = Request::CLREX|3|Request::LLSC; fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); } } else { -- cgit v1.2.3