From f9d1bba22a9e73ab45c0e255ca70eb509915181a Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:08 -0500
Subject: ARM: Add a version of the Dest and Op1 operands for accessing the
 MiscRegs.

---
 src/arch/arm/isa/operands.isa | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/arch/arm/isa')

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index e2b73e2e2..903982f29 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -94,12 +94,14 @@ def operands {{
                maybePCRead, maybeIWPCWrite),
     'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
                 maybePCRead, maybeAIWPCWrite),
+    'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 0),
     'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
              maybeAlignedPCRead, maybePCWrite),
     'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
               maybePCRead, maybePCWrite),
     'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
               maybePCRead, maybePCWrite),
+    'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 0),
     'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
               maybePCRead, maybePCWrite),
     'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4,
-- 
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