From 612f8f074fa1099cf70faf495d46cc647762a031 Mon Sep 17 00:00:00 2001 From: ARM gem5 Developers Date: Fri, 24 Jan 2014 15:29:34 -0600 Subject: arm: Add support for ARMv8 (AArch64 & AArch32) Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black --- src/arch/arm/isa_traits.hh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/arch/arm/isa_traits.hh') diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh index 742ca2037..506c5009c 100644 --- a/src/arch/arm/isa_traits.hh +++ b/src/arch/arm/isa_traits.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010, 2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -95,6 +95,9 @@ namespace ArmISA const Addr PAddrImplMask = (ULL(1) << PABits) - 1; + // Max. physical address range in bits supported by the architecture + const unsigned MaxPhysAddrRange = 48; + // return a no-op instruction... used for instruction fetch faults const ExtMachInst NoopMachInst = 0x01E320F000ULL; @@ -124,6 +127,8 @@ namespace ArmISA INT_IRQ, INT_FIQ, INT_SEV, // Special interrupt for recieving SEV's + INT_VIRT_IRQ, + INT_VIRT_FIQ, NumInterruptTypes }; } // namespace ArmISA -- cgit v1.2.3