From 7c4eb3b4d88480003f8c227731f7a31bd55cb819 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 1 Jun 2015 19:44:19 +0100 Subject: kvm, arm: Add support for aarch64 This changeset adds support for aarch64 in kvm. The CPU module supports both checkpointing and online CPU model switching as long as no devices are simulated by the host kernel. It currently has the following limitations: * The system register based generic timer can only be simulated by the host kernel. Workaround: Use a memory mapped timer instead to simulate the timer in gem5. * Simulating devices (e.g., the generic timer) in the host kernel requires that the host kernel also simulates the GIC. * ID registers in the host and in gem5 must match for switching between simulated CPUs and KVM. This is particularly important for ID registers describing memory system capabilities (e.g., ASID size, physical address size). * Switching between a virtualized CPU and a simulated CPU is currently not supported if in-kernel device emulation is used. This could be worked around by adding support for switching to the gem5 (e.g., the KvmGic) side of the device models. A simpler workaround is to avoid in-kernel device models altogether. --- src/arch/arm/kvm/SConscript | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/arch/arm/kvm/SConscript') diff --git a/src/arch/arm/kvm/SConscript b/src/arch/arm/kvm/SConscript index 185aac7b6..a8a2d2dc8 100644 --- a/src/arch/arm/kvm/SConscript +++ b/src/arch/arm/kvm/SConscript @@ -48,6 +48,12 @@ host_isa = platform.machine() SimObject('KvmGic.py') Source('gic.cc') +SimObject('BaseArmKvmCPU.py') +Source('base_cpu.cc') + if host_isa == "armv7l": SimObject('ArmKvmCPU.py') Source('arm_cpu.cc') +elif host_isa == "aarch64": + SimObject('ArmV8KvmCPU.py') + Source('armv8_cpu.cc') -- cgit v1.2.3