From baf88e908d285191c13b5e96c16065957e5af7a6 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 29 Oct 2014 23:18:26 -0500
Subject: arm: Fix multi-system AArch64 boot w/caches.

Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.
---
 src/arch/arm/linux/system.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/arch/arm/linux/system.cc')

diff --git a/src/arch/arm/linux/system.cc b/src/arch/arm/linux/system.cc
index 216a65899..66278681d 100644
--- a/src/arch/arm/linux/system.cc
+++ b/src/arch/arm/linux/system.cc
@@ -175,6 +175,10 @@ LinuxArmSystem::initState()
                  "to DTB file: %s\n", params()->dtb_filename);
         }
 
+        Addr ra = _dtb_file->findReleaseAddr();
+        if (ra)
+            bootReleaseAddr = ra & ~ULL(0x7F);
+
         dtb_file->setTextBase(params()->atags_addr + loadAddrOffset);
         dtb_file->loadSections(physProxy);
         delete dtb_file;
-- 
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