From 23b9792681d4cd794b0ad74138160a37b8bdac8f Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Tue, 5 May 2015 03:22:30 -0400
Subject: arm: Remove unnecessary boot uncachability

With the recent patches addressing how we deal with uncacheable
accesses there is no longer need for the work arounds put in place to
enforce certain sections of memory to be uncacheable during boot.
---
 src/arch/arm/linux/system.cc | 35 +----------------------------------
 src/arch/arm/linux/system.hh | 12 ------------
 2 files changed, 1 insertion(+), 46 deletions(-)

(limited to 'src/arch/arm/linux')

diff --git a/src/arch/arm/linux/system.cc b/src/arch/arm/linux/system.cc
index 216e9ddc0..f6df6307a 100644
--- a/src/arch/arm/linux/system.cc
+++ b/src/arch/arm/linux/system.cc
@@ -63,8 +63,7 @@ using namespace Linux;
 LinuxArmSystem::LinuxArmSystem(Params *p)
     : GenericArmSystem(p), dumpStatsPCEvent(nullptr),
       enableContextSwitchStatsDump(p->enable_context_switch_stats_dump),
-      taskFile(nullptr), kernelPanicEvent(nullptr), kernelOopsEvent(nullptr),
-      bootReleaseAddr(p->boot_release_addr)
+      taskFile(nullptr), kernelPanicEvent(nullptr), kernelOopsEvent(nullptr)
 {
     if (p->panic_on_panic) {
         kernelPanicEvent = addKernelFuncEventOrPanic<PanicPCEvent>(
@@ -96,34 +95,6 @@ LinuxArmSystem::LinuxArmSystem(Params *p)
         constUDelaySkipEvent = addKernelFuncEventOrPanic<UDelayEvent>(
          "__const_udelay", "__const_udelay", 1000, 107374);
 
-    secDataPtrAddr = 0;
-    secDataAddr = 0;
-    penReleaseAddr = 0;
-
-    kernelSymtab->findAddress("__secondary_data", secDataPtrAddr);
-    kernelSymtab->findAddress("secondary_data", secDataAddr);
-    kernelSymtab->findAddress("pen_release", penReleaseAddr);
-    kernelSymtab->findAddress("secondary_holding_pen_release", pen64ReleaseAddr);
-
-    secDataPtrAddr &= ~ULL(0x7F);
-    secDataAddr &= ~ULL(0x7F);
-    penReleaseAddr &= ~ULL(0x7F);
-    pen64ReleaseAddr &= ~ULL(0x7F);
-    bootReleaseAddr = (bootReleaseAddr & ~ULL(0x7F)) + loadAddrOffset;
-
-}
-
-bool
-LinuxArmSystem::adderBootUncacheable(Addr a)
-{
-    Addr block = a & ~ULL(0x7F);
-
-    if (block == secDataPtrAddr || block == secDataAddr ||
-            block == penReleaseAddr || pen64ReleaseAddr == block ||
-            block == bootReleaseAddr)
-        return true;
-
-    return false;
 }
 
 void
@@ -175,10 +146,6 @@ LinuxArmSystem::initState()
                  "to DTB file: %s\n", params()->dtb_filename);
         }
 
-        Addr ra = _dtb_file->findReleaseAddr();
-        if (ra)
-            bootReleaseAddr = ra & ~ULL(0x7F);
-
         dtb_file->setTextBase(params()->atags_addr + loadAddrOffset);
         dtb_file->loadSections(physProxy);
         delete dtb_file;
diff --git a/src/arch/arm/linux/system.hh b/src/arch/arm/linux/system.hh
index 32e3568b3..388c1e70a 100644
--- a/src/arch/arm/linux/system.hh
+++ b/src/arch/arm/linux/system.hh
@@ -89,8 +89,6 @@ class LinuxArmSystem : public GenericArmSystem
 
     void initState();
 
-    bool adderBootUncacheable(Addr a);
-
     void startup();
 
     /** This function creates a new task Id for the given pid.
@@ -118,16 +116,6 @@ class LinuxArmSystem : public GenericArmSystem
      */
     Linux::UDelayEvent *constUDelaySkipEvent;
 
-    /** These variables store addresses of important data structures
-     * that are normaly kept coherent at boot with cache mainetence operations.
-     * Since these operations aren't supported in gem5, we keep them coherent
-     * by making them uncacheable until all processors in the system boot.
-     */
-    Addr secDataPtrAddr;
-    Addr secDataAddr;
-    Addr penReleaseAddr;
-    Addr pen64ReleaseAddr;
-    Addr bootReleaseAddr;
 };
 
 class DumpStatsPCEvent : public PCEvent
-- 
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