From 282cf5807d827d5583e5cd5bffae75c4e5efb116 Mon Sep 17 00:00:00 2001 From: Curtis Dunham Date: Mon, 19 Dec 2016 11:03:27 -0600 Subject: arm: miscreg refactoring Change-Id: I4e9e8f264a4a4239dd135a6c7a1c8da213b6d345 Reviewed-by: Andreas Sandberg --- src/arch/arm/miscregs.cc | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'src/arch/arm/miscregs.cc') diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index c4915cb54..525d44810 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -2039,12 +2039,8 @@ canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) int flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc) { - int reg_as_int = static_cast(reg); - if (miscRegInfo[reg][MISCREG_BANKED]) { - SCR scr = tc->readMiscReg(MISCREG_SCR); - reg_as_int += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1; - } - return reg_as_int; + SCR scr = tc->readMiscReg(MISCREG_SCR); + return flattenMiscRegNsBanked(reg, tc, scr.ns); } int @@ -2052,7 +2048,8 @@ flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns) { int reg_as_int = static_cast(reg); if (miscRegInfo[reg][MISCREG_BANKED]) { - reg_as_int += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1; + reg_as_int += (ArmSystem::haveSecurity(tc) && + !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1; } return reg_as_int; } -- cgit v1.2.3