From 30746da58f3dbcb37df6214999ad48cb7df1cc4a Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 25 Sep 2018 17:37:06 +0100 Subject: arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register This patch implements AArch64 Memory Model Feature Register 2 (from ARMv8.2) Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/13066 Maintainer: Andreas Sandberg --- src/arch/arm/miscregs.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/arch/arm/miscregs.cc') diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index bbd5347e5..07123bd7d 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1539,7 +1539,9 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_ID_AA64MMFR0_EL1; case 1: return MISCREG_ID_AA64MMFR1_EL1; - case 2 ... 7: + case 2: + return MISCREG_ID_AA64MMFR2_EL1; + case 3 ... 7: return MISCREG_RAZ; } break; @@ -3504,6 +3506,8 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_AA64MMFR1_EL1) .allPrivileges().exceptUserMode().writes(0); + InitReg(MISCREG_ID_AA64MMFR2_EL1) + .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_CCSIDR_EL1) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_CLIDR_EL1) -- cgit v1.2.3