From 89b3397cf0daba4b2a339e26183aa82e1a573ad0 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 20 Apr 2018 09:50:29 +0100 Subject: arch-arm: Implement ARMv8.1 TTBR1_EL2 register This patch implements the ARMv8.1 TTBR1_EL2 register, which is used for getting the translation table base address when a Host Operating System is running at EL2. (HCR_EL2.E2H = 1) Change-Id: Ic0ab351cae3fd64855eda7c18c8757da0d7b8663 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10382 Maintainer: Andreas Sandberg --- src/arch/arm/miscregs.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/arm/miscregs.cc') diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 08eb255f3..e1ddbf9d3 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -3535,7 +3535,7 @@ ISA::initializeMiscRegMetadata() .hyp().mon() .mapsTo(MISCREG_HTTBR); InitReg(MISCREG_TTBR1_EL2) - .unimplemented(); + .hyp().mon(); InitReg(MISCREG_TCR_EL2) .hyp().mon() .mapsTo(MISCREG_HTCR); -- cgit v1.2.3