From 16fcad3907f439b8cdbaad638a8618ee7ad6a9da Mon Sep 17 00:00:00 2001
From: William Wang <William.Wang@arm.com>
Date: Mon, 4 Apr 2011 11:42:28 -0500
Subject: ARM: Cleanup and small fixes to some NEON ops to match the spec.

Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
---
 src/arch/arm/miscregs.hh | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/arch/arm/miscregs.hh')

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 1e105799f..fc18fa114 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -310,6 +310,7 @@ namespace ArmISA
         Bitfield<23, 22> cp11;
         Bitfield<25, 24> cp12;
         Bitfield<27, 26> cp13;
+        Bitfield<29, 28> rsvd;
         Bitfield<30> d32dis;
         Bitfield<31> asedis;
     EndBitUnion(CPACR)
-- 
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