From 2eb6b403c976c7909a065b70ef831f4a309455b3 Mon Sep 17 00:00:00 2001 From: Anthony Gutierrez Date: Fri, 27 Jul 2012 16:08:04 -0400 Subject: ARM: fix value of MISCREG_CTR returned by readMiscReg() According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines) [31:29] Format - b100 specifies v7 [28] RAZ - b0 [27:24] CWG log2(max writeback size #words) - 0x4 16 words [23:20] ERG log2(max reservation size #words) - 0x4 16 words [19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words [15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT [13:4] RAZ - b0000000000 [3:0] IminLine log2(smallest icache line #words) - 0x4 16 words --- src/arch/arm/miscregs.hh | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/arch/arm/miscregs.hh') diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 0969479ee..7af4ec605 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -529,6 +529,16 @@ namespace ArmISA Bitfield<31> l2rstDISABLE_monitor; EndBitUnion(L2CTLR) + BitUnion32(CTR) + Bitfield<3,0> iCacheLineSize; + Bitfield<13,4> raz_13_4; + Bitfield<15,14> l1IndexPolicy; + Bitfield<19,16> dCacheLineSize; + Bitfield<23,20> erg; + Bitfield<27,24> cwg; + Bitfield<28> raz_28; + Bitfield<31,29> format; + EndBitUnion(CTR) } #endif // __ARCH_ARM_MISCREGS_HH__ -- cgit v1.2.3