From 401165c778108ab22aeeee55c4f4451ca93bcffb Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 13 May 2011 17:27:01 -0500 Subject: ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. --- src/arch/arm/miscregs.hh | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/arch/arm/miscregs.hh') diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 7f16924f2..5fe762ebe 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -251,8 +251,7 @@ namespace ArmISA }; BitUnion32(CPSR) - Bitfield<31> n; - Bitfield<30> z; + Bitfield<31,30> nz; Bitfield<29> c; Bitfield<28> v; Bitfield<27> q; @@ -271,9 +270,7 @@ namespace ArmISA // This mask selects bits of the CPSR that actually go in the CondCodes // integer register to allow renaming. static const uint32_t CondCodesMask = 0xF00F0000; - static const uint32_t CondCodesMaskF = 0xF0000000; static const uint32_t CpsrMaskQ = 0x08000000; - static const uint32_t CondCodesMaskGE = 0x000F0000; BitUnion32(SCTLR) Bitfield<31> ie; // Instruction endianness -- cgit v1.2.3