From 4a3f11149d791284a012af71067f6b2199aa165c Mon Sep 17 00:00:00 2001 From: Curtis Dunham Date: Tue, 29 Apr 2014 16:05:02 -0500 Subject: arm: use condition code registers for ARM ISA Analogous to ee049bf (for x86). Requires a bump of the checkpoint version and corresponding upgrader code to move the condition code register values to the new register file. --- src/arch/arm/miscregs.hh | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'src/arch/arm/miscregs.hh') diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 938df5688..e14722028 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -53,25 +53,6 @@ class ThreadContext; namespace ArmISA { - enum ConditionCode { - COND_EQ = 0, - COND_NE, // 1 - COND_CS, // 2 - COND_CC, // 3 - COND_MI, // 4 - COND_PL, // 5 - COND_VS, // 6 - COND_VC, // 7 - COND_HI, // 8 - COND_LS, // 9 - COND_GE, // 10 - COND_LT, // 11 - COND_GT, // 12 - COND_LE, // 13 - COND_AL, // 14 - COND_UC // 15 - }; - enum MiscRegIndex { MISCREG_CPSR = 0, // 0 MISCREG_SPSR, // 1 -- cgit v1.2.3