From 6c8dd32fa4f21771a2c83886b08c3d68be516044 Mon Sep 17 00:00:00 2001
From: Dam Sunwoo <dam.sunwoo@arm.com>
Date: Wed, 2 Jun 2010 12:58:18 -0500
Subject: ARM: Added support for Access Flag and some CP15 regs (V2PCWPR,
 V2PCWPW, V2PCWUR, V2PCWUW,...)

---
 src/arch/arm/miscregs.hh | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

(limited to 'src/arch/arm/miscregs.hh')

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index ad8f01dd0..267626e74 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -138,6 +138,15 @@ namespace ArmISA
         MISCREG_CTR,
         MISCREG_SCR,
         MISCREG_SDER,
+        MISCREG_PAR,
+        MISCREG_V2PCWPR,
+        MISCREG_V2PCWPW,
+        MISCREG_V2PCWUR,
+        MISCREG_V2PCWUW,
+        MISCREG_V2POWPR,
+        MISCREG_V2POWPW,
+        MISCREG_V2POWUR,
+        MISCREG_V2POWUW,
         MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
         MISCREG_ID_PFR1,
@@ -153,7 +162,6 @@ namespace ArmISA
         MISCREG_ID_ISAR3,
         MISCREG_ID_ISAR4,
         MISCREG_ID_ISAR5,
-        MISCREG_PAR,
         MISCREG_AIDR,
         MISCREG_ACTLR,
         MISCREG_ADFSR,
@@ -163,14 +171,6 @@ namespace ArmISA
         MISCREG_MCCSW,
         MISCREG_DCCMVAU,
         MISCREG_NSACR,
-        MISCREG_V2PCWPR,
-        MISCREG_V2PCWPW,
-        MISCREG_V2PCWUR,
-        MISCREG_V2PCWUW,
-        MISCREG_V2POWPR,
-        MISCREG_V2POWPW,
-        MISCREG_V2POWUR,
-        MISCREG_V2POWUW,
         MISCREG_VBAR,
         MISCREG_MVBAR,
         MISCREG_ISR,
@@ -206,20 +206,20 @@ namespace ArmISA
         "dtlbiall", "dtlbimva", "dtlbiasid",
         "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
         "dfsr", "ifsr", "dfar", "ifar", "mpidr",
-        "prrr", "nmrr",  "ttbcr", "id_pfr0", "ctr"
-        "scr", "sder"
+        "prrr", "nmrr",  "ttbcr", "id_pfr0", "ctr",
+        "scr", "sder", "par",
+        "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
+        "v2powpr", "v2powpw", "v2powur", "v2powuw",
         // Unimplemented below
         "tcmtr",
         "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
-        "par", "aidr", "actlr",
+        "aidr", "actlr",
         "adfsr", "aifsr",
         "dcimvac", "dcisw", "mccsw",
         "dccmvau",
         "nsacr",
-        "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
-        "v2powpr", "v2powpw", "v2powur", "v2powuw",
         "vbar", "mvbar", "isr", "fceidr",
         "nop", "raz"
     };
-- 
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