From 7c479d734922d0b9dd5c9b4404ef6d62b3d91075 Mon Sep 17 00:00:00 2001
From: Chander Sudanthi <Chander.Sudanthi@ARM.com>
Date: Tue, 13 Sep 2011 12:06:13 -0500
Subject: CP15 c15: enable execution with accesses to c15 registers

Previously, coprocessor accesses to CP15 c15 would fault.  This patch
enables accesses but prints out a warning, as the registers are not implemented.
---
 src/arch/arm/miscregs.hh | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/arch/arm/miscregs.hh')

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index f99748622..5e5735de7 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -196,6 +196,7 @@ namespace ArmISA
         MISCREG_ISR,
         MISCREG_FCEIDR,
         MISCREG_L2LATENCY,
+        MISCREG_CRN15,
 
 
         MISCREG_CP15_END,
@@ -249,6 +250,7 @@ namespace ArmISA
         "dccmvau",
         "nsacr",
         "vbar", "mvbar", "isr", "fceidr", "l2latency",
+        "crn15",
         "nop", "raz"
     };
 
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