From b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 2 Jun 2010 12:58:16 -0500
Subject: ARM: Implement ARM CPU interrupts

---
 src/arch/arm/miscregs.hh | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/arch/arm/miscregs.hh')

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 27f12c3b2..cdead8710 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -80,6 +80,7 @@ namespace ArmISA
         MISCREG_FPEXC,
         MISCREG_MVFR0,
         MISCREG_MVFR1,
+        MISCREG_SCTLR_RST,
         MISCREG_SEV_MAILBOX,
 
         // CP15 registers
@@ -191,7 +192,7 @@ namespace ArmISA
         "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
         "spsr_mon", "spsr_und", "spsr_abt",
         "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
-        "sev_mailbox",
+        "sctlr_rst", "sev_mailbox",
         "sctlr", "dccisw", "dccimvac", "dccmvac",
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
         "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
-- 
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