From e2ab64543b2a206c95fbf38565a50f0d5bba0f2a Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 14 Nov 2009 19:22:30 -0800
Subject: ARM: Define a mask to differentiate purely CPSR bits from CondCodes
 bits.

---
 src/arch/arm/miscregs.hh | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/arch/arm/miscregs.hh')

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 45233a764..d100efb8e 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -93,6 +93,10 @@ namespace ArmISA
         Bitfield<4, 0> mode;
     EndBitUnion(CPSR)
 
+    // This mask selects bits of the CPSR that actually go in the CondCodes
+    // integer register to allow renaming.
+    static const uint32_t CondCodesMask = 0xF80F0000;
+
     BitUnion32(SCTLR)
         Bitfield<30> te;  // Thumb Exception Enable
         Bitfield<29> afe; // Access flag enable
-- 
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