From 401165c778108ab22aeeee55c4f4451ca93bcffb Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 13 May 2011 17:27:01 -0500 Subject: ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. --- src/arch/arm/nativetrace.cc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src/arch/arm/nativetrace.cc') diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc index bc42f8e9d..e276833e2 100644 --- a/src/arch/arm/nativetrace.cc +++ b/src/arch/arm/nativetrace.cc @@ -115,9 +115,13 @@ Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]); //CPSR - newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) | - tc->readIntReg(INTREG_CONDCODES_F) | - tc->readIntReg(INTREG_CONDCODES_GE); + CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); + cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ); + cpsr.c = tc->readIntReg(INTREG_CONDCODES_C); + cpsr.v = tc->readIntReg(INTREG_CONDCODES_V); + cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE); + + newState[STATE_CPSR] = cpsr; changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); for (int i = 0; i < NumFloatArchRegs; i += 2) { -- cgit v1.2.3