From 3f835d88a337c74869393b76ef3c398c324754cc Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Tue, 2 May 2017 17:26:34 +0100 Subject: arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU The PMU model currently doesn't calculate the PMU event counter index correctly for writes to the PMEVTYPER[0-5]_EL0 registers. Fix this obvious mistake. Change-Id: I2913eedddeb98480660e2d63948f6d727adf5ab8 Signed-off-by: Andreas Sandberg Reviewed-by: Sudhanshu Jha Reviewed-on: https://gem5-review.googlesource.com/3121 Reviewed-by: Curtis Dunham --- src/arch/arm/pmu.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/arm/pmu.cc') diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc index 39530702c..ac2f4759f 100644 --- a/src/arch/arm/pmu.cc +++ b/src/arch/arm/pmu.cc @@ -163,7 +163,7 @@ PMU::setMiscReg(int misc_reg, MiscReg val) return; case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0: - setCounterTypeRegister(misc_reg - MISCREG_PMEVCNTR0_EL0, val); + setCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0_EL0, val); return; case MISCREG_PMCCFILTR: -- cgit v1.2.3