From 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 Mon Sep 17 00:00:00 2001
From: Stephen Hines <hines@cs.fsu.edu>
Date: Sun, 5 Apr 2009 18:53:15 -0700
Subject: arm: add ARM support to M5

---
 src/arch/arm/regfile/regfile.cc | 86 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)
 create mode 100644 src/arch/arm/regfile/regfile.cc

(limited to 'src/arch/arm/regfile/regfile.cc')

diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc
new file mode 100644
index 000000000..5de0b3076
--- /dev/null
+++ b/src/arch/arm/regfile/regfile.cc
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Stephen Hines
+ */
+
+#include "arch/arm/regfile/regfile.hh"
+#include "sim/serialize.hh"
+
+using namespace std;
+
+namespace ArmISA
+{
+
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Regs Not Implemented Yet\n");
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Misc. Regs Not Implemented Yet\n");
+}
+
+void
+MiscRegFile::copyMiscRegs(ThreadContext *tc)
+{
+    panic("Copy Misc. Regs Not Implemented Yet\n");
+}
+
+void
+RegFile::serialize(std::ostream &os)
+{
+    intRegFile.serialize(os);
+    //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
+    //SERIALZE_ARRAY(miscRegFile);
+    //SERIALIZE_SCALAR(miscRegs.fpcr);
+    //SERIALIZE_SCALAR(miscRegs.lock_flag);
+    //SERIALIZE_SCALAR(miscRegs.lock_addr);
+    //SERIALIZE_SCALAR(pc);
+    SERIALIZE_SCALAR(npc);
+    SERIALIZE_SCALAR(nnpc);
+}
+
+void
+RegFile::unserialize(Checkpoint *cp, const std::string &section)
+{
+    intRegFile.unserialize(cp, section);
+    //UNSERIALIZE_ARRAY(floatRegFile);
+    //UNSERIALZE_ARRAY(miscRegFile);
+    //UNSERIALIZE_SCALAR(miscRegs.fpcr);
+    //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
+    //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
+    //UNSERIALIZE_SCALAR(pc);
+    UNSERIALIZE_SCALAR(npc);
+    UNSERIALIZE_SCALAR(nnpc);
+
+}
+
+} // namespace ArmISA
-- 
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