From 25474167e5b247d1b91fbf802c5b396a63ae705e Mon Sep 17 00:00:00 2001 From: Giacomo Gabrielli Date: Tue, 16 Oct 2018 16:04:08 +0100 Subject: arch,cpu: Add vector predicate registers Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector Extension (SVE), introduce the notion of a predicate register file. This changeset adds this feature across architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/c/13715 Maintainer: Andreas Sandberg Reviewed-by: Jason Lowe-Power --- src/arch/arm/registers.hh | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'src/arch/arm/registers.hh') diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index 8346f454b..8960f9f92 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -47,6 +47,8 @@ #include "arch/arm/generated/max_inst_regs.hh" #include "arch/arm/intregs.hh" #include "arch/arm/miscregs.hh" +#include "arch/arm/types.hh" +#include "arch/generic/vec_pred_reg.hh" #include "arch/generic/vec_reg.hh" namespace ArmISA { @@ -66,6 +68,15 @@ using VecReg = ::VecRegT; using ConstVecReg = ::VecRegT; using VecRegContainer = VecReg::Container; +constexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem); + +// Dummy typedefs +using VecPredReg = ::DummyVecPredReg; +using ConstVecPredReg = ::DummyConstVecPredReg; +using VecPredRegContainer = ::DummyVecPredRegContainer; +constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits; +constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; + // condition code register; must be at least 32 bits for FpCondCodes typedef uint64_t CCReg; @@ -82,12 +93,14 @@ const int NumVecSpecialRegs = 8; const int NumIntRegs = NUM_INTREGS; const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs; +const int NumVecPredRegs = 1; const int NumCCRegs = NUM_CCREGS; const int NumMiscRegs = NUM_MISCREGS; #define ISA_HAS_CC_REGS -const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + NumMiscRegs; +const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + + NumVecPredRegs + NumMiscRegs; // semantically meaningful register indices const int ReturnValueReg = 0; -- cgit v1.2.3