From 91295ff980c17efb3ad013b9636017b58e49c071 Mon Sep 17 00:00:00 2001 From: Anouk Van Laer Date: Tue, 4 Sep 2018 11:44:42 +0100 Subject: arch-arm: Correction for address size in EL1&0 translation When doing EL0/1 translation in stage2, the physical address size will be defined by the hypervisor (via VTCR_EL2.ps, not TCR.ips). See D10.2.121 of the ARM ARM. Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/12552 Maintainer: Giacomo Travaglini --- src/arch/arm/table_walker.cc | 49 +++++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 23 deletions(-) (limited to 'src/arch/arm/table_walker.cc') diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 66714fff8..1a7b5d375 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -771,30 +771,33 @@ TableWalker::processWalkAArch64() start_lookup_level = SLL[sl_tg]; panic_if(start_lookup_level == MAX_LOOKUP_LEVELS, "Cannot discern lookup level from vtcr.{sl0,tg0}"); - } else switch (bits(currState->vaddr, 63,48)) { - case 0: - DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); - ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); - tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); - tg = GrainMap_tg0[currState->tcr.tg0]; - if (bits(currState->vaddr, 63, tsz) != 0x0 || - currState->tcr.epd0) - fault = true; - break; - case 0xffff: - DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); - ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); - tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); - tg = GrainMap_tg1[currState->tcr.tg1]; - if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || - currState->tcr.epd1) - fault = true; - break; - default: - // top two bytes must be all 0s or all 1s, else invalid addr - fault = true; + ps = currState->vtcr.ps; + } else { + switch (bits(currState->vaddr, 63,48)) { + case 0: + DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n"); + ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1); + tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz); + tg = GrainMap_tg0[currState->tcr.tg0]; + if (bits(currState->vaddr, 63, tsz) != 0x0 || + currState->tcr.epd0) + fault = true; + break; + case 0xffff: + DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n"); + ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1); + tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz); + tg = GrainMap_tg1[currState->tcr.tg1]; + if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) || + currState->tcr.epd1) + fault = true; + break; + default: + // top two bytes must be all 0s or all 1s, else invalid addr + fault = true; + } + ps = currState->tcr.ips; } - ps = currState->tcr.ips; break; case EL2: switch(bits(currState->vaddr, 63,48)) { -- cgit v1.2.3