From 31fd18ab156f86ec2fced0641d2c76fba60a7d2d Mon Sep 17 00:00:00 2001 From: Nathanael Premillieu Date: Tue, 26 May 2015 03:21:42 -0400 Subject: arm: Make address translation faster with better caching This patch adds better caching of the sys regs for AArch64, thus avoiding unnecessary calls to tc->readMiscReg(MISCREG_CPSR) in the non-faulting case. --- src/arch/arm/tlb.cc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'src/arch/arm/tlb.cc') diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 61c2eb9d6..dfda14d30 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -546,7 +546,7 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, Addr vaddr_tainted = req->getVaddr(); Addr vaddr = 0; if (aarch64) - vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); + vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); else vaddr = vaddr_tainted; uint32_t flags = req->getFlags(); @@ -765,7 +765,7 @@ TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, assert(aarch64); Addr vaddr_tainted = req->getVaddr(); - Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); + Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); uint32_t flags = req->getFlags(); bool is_fetch = (mode == Execute); @@ -959,7 +959,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, Addr vaddr_tainted = req->getVaddr(); Addr vaddr = 0; if (aarch64) - vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); + vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); else vaddr = vaddr_tainted; uint32_t flags = req->getFlags(); @@ -1110,7 +1110,6 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, // Generate Illegal Inst Set State fault if IL bit is set in CPSR if (fault == NoFault) { - CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); if (aarch64 && is_fetch && cpsr.il == 1) { return std::make_shared(); } @@ -1222,7 +1221,7 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) } DPRINTF(TLBVerbose, "TLB variables changed!\n"); - CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); + cpsr = tc->readMiscReg(MISCREG_CPSR); // Dependencies: SCR/SCR_EL3, CPSR isSecure = inSecureState(tc); isSecure &= (tranType & HypMode) == 0; @@ -1328,7 +1327,7 @@ TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, Addr vaddr = 0; ExceptionLevel target_el = aarch64 ? aarch64EL : EL1; if (aarch64) { - vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el); + vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el, ttbcr); } else { vaddr = vaddr_tainted; } -- cgit v1.2.3