From 4325519fc5d1cf2bf4e57edebc739b9f79446267 Mon Sep 17 00:00:00 2001
From: Dam Sunwoo <dam.sunwoo@arm.com>
Date: Wed, 2 Jun 2010 12:58:18 -0500
Subject: ARM: Allow multiple outstanding TLB walks to queue.

---
 src/arch/arm/tlb.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/arch/arm/tlb.cc')

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index acc6b416b..f0e40f690 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -387,7 +387,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
 
         // Set memory attributes
         TlbEntry temp_te;
-        tableWalker->memAttrs(tc, temp_te, 0, 1);
+        tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
         temp_te.shareable = true;
         DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
                 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
-- 
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