From 706597f021811511e71fddeeab7dcfc33bfd5f35 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Tue, 5 May 2015 03:22:34 -0400 Subject: arm: Relax ordering for some uncacheable accesses We currently assume that all uncacheable memory accesses are strictly ordered. Instead of always enforcing strict ordering, we now only enforce it if the required memory type is device memory or strongly ordered memory. --- src/arch/arm/tlb.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src/arch/arm/tlb.cc') diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 8c3bb047d..61c2eb9d6 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1076,7 +1076,13 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, setAttr(te->attributes); if (te->nonCacheable) - req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); + req->setFlags(Request::UNCACHEABLE); + + // Require requests to be ordered if the request goes to + // strongly ordered or device memory (i.e., anything other + // than normal memory requires strict order). + if (te->mtype != TlbEntry::MemoryType::Normal) + req->setFlags(Request::STRICT_ORDER); Addr pa = te->pAddr(vaddr); req->setPaddr(pa); -- cgit v1.2.3