From 85e8779de78ed913bb6d2a794bee5252d719b0e5 Mon Sep 17 00:00:00 2001
From: Dam Sunwoo <dam.sunwoo@arm.com>
Date: Fri, 24 Jan 2014 15:29:30 -0600
Subject: mem: per-thread cache occupancy and per-block ages

This patch enables tracking of cache occupancy per thread along with
ages (in buckets) per cache blocks.  Cache occupancy stats are
recalculated on each stat dump.
---
 src/arch/arm/tlb.cc | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/arch/arm/tlb.cc')

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 107901f99..805898576 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -54,6 +54,7 @@
 #include "base/inifile.hh"
 #include "base/str.hh"
 #include "base/trace.hh"
+#include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Checkpoint.hh"
 #include "debug/TLB.hh"
@@ -477,6 +478,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
     if (is_priv)
         req->setFlags(Request::PRIVILEGED);
 
+    req->taskId(tc->getCpuPtr()->taskId());
+
     DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
             isPriv, flags & UserMode);
     // If this is a clrex instruction, provide a PA of 0 with no fault
-- 
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