From cbb23a1d3c3df9d6bed34f50a0193b93319477e6 Mon Sep 17 00:00:00 2001
From: Daniel Johnson <daniel.johnson@arm.com>
Date: Tue, 13 Sep 2011 12:06:13 -0500
Subject: ARM: update TLB to set request packet ASID field

---
 src/arch/arm/tlb.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/arch/arm/tlb.cc')

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 942f85120..a03e445cf 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -467,6 +467,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
     bool is_write = (mode == Write);
     bool is_priv = isPriv && !(flags & UserMode);
 
+    req->setAsid(contextId.asid);
+
     DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
             isPriv, flags & UserMode);
     // If this is a clrex instruction, provide a PA of 0 with no fault
-- 
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