From d6736384b2bb280ec12d472cac6eb25a70b4af60 Mon Sep 17 00:00:00 2001
From: Gene Wu <Gene.Wu@arm.com>
Date: Mon, 23 Aug 2010 11:18:41 -0500
Subject: MEM: Make CLREX a first class request operation and clear locks in
 caches when it in received

---
 src/arch/arm/tlb.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/arch/arm/tlb.cc')

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a70a20518..a48805c81 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -358,9 +358,10 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
     // If this is a clrex instruction, provide a PA of 0 with no fault
     // This will force the monitor to set the tracked address to 0
     // a bit of a hack but this effectively clrears this processors monitor
-    if (flags & Clrex){
+    if (flags & Request::CLREX){
        req->setPaddr(0);
        req->setFlags(Request::UNCACHEABLE);
+       req->setFlags(Request::CLREX);
        return NoFault;
     }
     if ((req->isInstFetch() && (!sctlr.i)) ||
-- 
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