From af6aaf258171027af8d3cf0ef86dddff501a3ccb Mon Sep 17 00:00:00 2001 From: Geoffrey Blake Date: Tue, 31 Jan 2012 07:46:03 -0800 Subject: CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 Brings the CheckerCPU back to life to allow FS and SE checking of the O3CPU. These changes have only been tested with the ARM ISA. Other ISAs potentially require modification. --- src/arch/arm/tlb.cc | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/tlb.cc') diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index a03e445cf..f4dc47655 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -453,8 +453,11 @@ TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, Fault TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, - Translation *translation, bool &delay, bool timing) + Translation *translation, bool &delay, bool timing, bool functional) { + // No such thing as a functional timing access + assert(!(timing && functional)); + if (!miscRegValid) { updateMiscReg(tc); DPRINTF(TLBVerbose, "TLB variables changed!\n"); @@ -541,7 +544,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", vaddr, contextId); fault = tableWalker->walk(req, tc, contextId, mode, translation, - timing); + timing, functional); if (timing && fault == NoFault) { delay = true; // for timing mode, return and wait for table walk @@ -700,6 +703,20 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) return fault; } +Fault +TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) +{ + bool delay = false; + Fault fault; +#if FULL_SYSTEM + fault = translateFs(req, tc, mode, NULL, delay, false, true); +#else + fault = translateSe(req, tc, mode, NULL, delay, false); +#endif + assert(!delay); + return fault; +} + Fault TLB::translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode) -- cgit v1.2.3