From fb52ea9220f307de18da6565a2cbbaf67ba2b7a7 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 7 Jan 2013 13:05:45 -0500 Subject: arm: Invalidate cached TLB configuration in drainResume Currently, we invalidate the cached miscregs in TLB::unserialize(). The intended use of the drainResume() method is to invalidate cached state and prepare the system to resume after a CPU handover or (un)serialization. This patch moves the TLB miscregs invalidation code to the drainResume() method to avoid surprising behavior. --- src/arch/arm/tlb.cc | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/tlb.cc') diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index e7ac935e6..170d819d8 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010-2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -252,6 +252,14 @@ TLB::flushMva(Addr mva) flushTlbMva++; } +void +TLB::drainResume() +{ + // We might have unserialized something or switched CPUs, so make + // sure to re-read the misc regs. + miscRegValid = false; +} + void TLB::serialize(ostream &os) { @@ -278,7 +286,6 @@ TLB::unserialize(Checkpoint *cp, const string §ion) for(int i = 0; i < min(size, num_entries); i++){ table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); } - miscRegValid = false; } void -- cgit v1.2.3