From 057b451773eb2f6042cf5a1f6d86b39a8a48eff5 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Mon, 8 Nov 2010 13:58:25 -0600
Subject: ARM: Add some TLB statistics for ARM

---
 src/arch/arm/tlb.hh | 28 ++++++++++++++++++++--------
 1 file changed, 20 insertions(+), 8 deletions(-)

(limited to 'src/arch/arm/tlb.hh')

diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index bd723e8d1..a6803c415 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -102,14 +102,26 @@ class TLB : public BaseTLB
     TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
 
     // Access Stats
-    mutable Stats::Scalar read_hits;
-    mutable Stats::Scalar read_misses;
-    mutable Stats::Scalar read_acv;
-    mutable Stats::Scalar read_accesses;
-    mutable Stats::Scalar write_hits;
-    mutable Stats::Scalar write_misses;
-    mutable Stats::Scalar write_acv;
-    mutable Stats::Scalar write_accesses;
+    mutable Stats::Scalar instHits;
+    mutable Stats::Scalar instMisses;
+    mutable Stats::Scalar readHits;
+    mutable Stats::Scalar readMisses;
+    mutable Stats::Scalar writeHits;
+    mutable Stats::Scalar writeMisses;
+    mutable Stats::Scalar inserts;
+    mutable Stats::Scalar flushTlb;
+    mutable Stats::Scalar flushTlbMva;
+    mutable Stats::Scalar flushTlbMvaAsid;
+    mutable Stats::Scalar flushTlbAsid;
+    mutable Stats::Scalar flushedEntries;
+    mutable Stats::Scalar alignFaults;
+    mutable Stats::Scalar prefetchFaults;
+    mutable Stats::Scalar domainFaults;
+    mutable Stats::Scalar permsFaults;
+
+    Stats::Formula readAccesses;
+    Stats::Formula writeAccesses;
+    Stats::Formula instAccesses;
     Stats::Formula hits;
     Stats::Formula misses;
     Stats::Formula accesses;
-- 
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