From 0e9da43cb63cb6876da608bef980d763d58e4381 Mon Sep 17 00:00:00 2001 From: Anouk Van Laer Date: Fri, 19 Oct 2018 11:19:08 +0100 Subject: arch, arm: Effect of AT instructions on descriptor handling Some address translation instructions will stop translation after the 1st stage and intercept the IPA, even in the presence of stage 2 (eg AT S1E1). However, in the case of a TLB miss, the table descriptors still need to be translated from IPA to PA to avoid fetching the wrong addresses. This commit splits whether IPA->PA translation is required for the VA and/or for the table descriptors. Change-Id: Ie53cdc00585f116150256f1d833460931b3bfb7d Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/13781 Maintainer: Andreas Sandberg --- src/arch/arm/tlb.hh | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/arch/arm/tlb.hh') diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 336b31b78..637240abb 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, 2016 ARM Limited + * Copyright (c) 2010-2013, 2016, 2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -152,6 +152,10 @@ class TLB : public BaseTLB int size; // TLB Size bool isStage2; // Indicates this TLB is part of the second stage MMU bool stage2Req; // Indicates whether a stage 2 lookup is also required + // Indicates whether a stage 2 lookup of the table descriptors is required. + // Certain address translation instructions will intercept the IPA but the + // table descriptors still need to be translated by the stage2. + bool stage2DescReq; uint64_t _attr; // Memory attributes for last accessed TLB entry bool directToStage2; // Indicates whether all translation requests should // be routed directly to the stage 2 TLB -- cgit v1.2.3