From 96cc03f90db82fa8f84248ef478362267dba292c Mon Sep 17 00:00:00 2001 From: Andrea Mondelli Date: Fri, 22 Feb 2019 11:29:10 -0500 Subject: mem-cache: alias to mem::getMasterPort in TLB class TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and hides the BaseTLB::getMasterPort(). The TLB::getMasterPort() is renamed according to the expected behavior. Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8 Reviewed-on: https://gem5-review.googlesource.com/c/16648 Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/arm/tlb.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/arm/tlb.hh') diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 637240abb..8ca176a82 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -401,7 +401,7 @@ class TLB : public BaseTLB * * @return A pointer to the walker master port */ - BaseMasterPort* getMasterPort() override; + BaseMasterPort* getTableWalkerMasterPort() override; // Caching misc register values here. // Writing to misc registers needs to invalidate them. -- cgit v1.2.3