From fb52ea9220f307de18da6565a2cbbaf67ba2b7a7 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 7 Jan 2013 13:05:45 -0500 Subject: arm: Invalidate cached TLB configuration in drainResume Currently, we invalidate the cached miscregs in TLB::unserialize(). The intended use of the drainResume() method is to invalidate cached state and prepare the system to resume after a CPU handover or (un)serialization. This patch moves the TLB miscregs invalidation code to the drainResume() method to avoid surprising behavior. --- src/arch/arm/tlb.hh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/arch/arm/tlb.hh') diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 968699764..f5c7320ed 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010-2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -208,6 +208,8 @@ class TLB : public BaseTLB Fault translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode); + void drainResume(); + // Checkpointing void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); -- cgit v1.2.3