From 17a0c0b00644c37e9d8539a9de0a02dc213a6834 Mon Sep 17 00:00:00 2001 From: Adrian Herrera Date: Fri, 8 Nov 2019 15:25:21 +0000 Subject: arch-arm: R/W interface to AArch32 HCR2 misc reg This patch implements read/write interfaces to HCR2 AArch32 register, which is mapped to the upper 32 bits of HCR_EL2. Change-Id: I996023f3ad8233457d19de8a506ebcf106409165 Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832 Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/tracers/tarmac_parser.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/arm/tracers') diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc index ce2300ed5..1495c7a74 100644 --- a/src/arch/arm/tracers/tarmac_parser.cc +++ b/src/arch/arm/tracers/tarmac_parser.cc @@ -168,6 +168,7 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = { { "hsctlr", MISCREG_HSCTLR }, { "hactlr", MISCREG_HACTLR }, { "hcr", MISCREG_HCR }, + { "hcr2", MISCREG_HCR2 }, { "hdcr", MISCREG_HDCR }, { "hcptr", MISCREG_HCPTR }, { "hstr", MISCREG_HSTR }, -- cgit v1.2.3