From 30746da58f3dbcb37df6214999ad48cb7df1cc4a Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 25 Sep 2018 17:37:06 +0100 Subject: arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register This patch implements AArch64 Memory Model Feature Register 2 (from ARMv8.2) Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/13066 Maintainer: Andreas Sandberg --- src/arch/arm/tracers/tarmac_parser.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/arm/tracers') diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc index 68738cba2..67bbb1493 100644 --- a/src/arch/arm/tracers/tarmac_parser.cc +++ b/src/arch/arm/tracers/tarmac_parser.cc @@ -415,6 +415,7 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = { { "id_aa64isar1_el1", MISCREG_ID_AA64ISAR1_EL1 }, { "id_aa64mmfr0_el1", MISCREG_ID_AA64MMFR0_EL1 }, { "id_aa64mmfr1_el1", MISCREG_ID_AA64MMFR1_EL1 }, + { "id_aa64mmfr2_el1", MISCREG_ID_AA64MMFR2_EL1 }, { "ccsidr_el1", MISCREG_CCSIDR_EL1 }, { "clidr_el1", MISCREG_CLIDR_EL1 }, { "aidr_el1", MISCREG_AIDR_EL1 }, -- cgit v1.2.3