From 6b6989049383b67a2daef562a0319421ff1a8067 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 4 Apr 2011 11:42:28 -0500 Subject: ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works. This change fixes a small bug in the arm copyRegs() code where some registers wouldn't be copied if the processor was in a mode other than MODE_USER. Additionally, this change simplifies the way the O3 switchCpu code works by utilizing TheISA::copyRegs() to copy the required context information rather than the adhoc copying that goes on in the CPU model. The current code makes assumptions about the visibility of int and float registers that aren't true for all architectures in FS mode. --- src/arch/arm/utility.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/arch/arm/utility.cc') diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 0d91c9f90..6bca63291 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -124,8 +124,21 @@ void copyRegs(ThreadContext *src, ThreadContext *dest) { int i; + + int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode; + + // Make sure we're in user mode, so we can easily see all the registers + // in the copy loop + src->setMiscReg(MISCREG_CPSR_MODE, MODE_USER); + dest->setMiscReg(MISCREG_CPSR_MODE, MODE_USER); + for(i = 0; i < TheISA::NumIntRegs; i++) dest->setIntReg(i, src->readIntReg(i)); + + // Restore us back to the old mode + src->setMiscReg(MISCREG_CPSR_MODE, saved_mode); + dest->setMiscReg(MISCREG_CPSR_MODE, saved_mode); + for(i = 0; i < TheISA::NumFloatRegs; i++) dest->setFloatReg(i, src->readFloatReg(i)); for(i = 0; i < TheISA::NumMiscRegs; i++) -- cgit v1.2.3