From ec9ce6239d0c3a4e6141961bfb9caae50b9caac9 Mon Sep 17 00:00:00 2001 From: Adrian Herrera Date: Wed, 6 Nov 2019 13:07:28 +0000 Subject: arch-arm: Secure EL2 checking This patch adds Armv8.4-SecEL2 checking. Helpers implementing EL2Enabled, IsSecureEL2Enabled and HaveSecureEL2Ext following the architecture pseudocode are provided. These are intended to be used for checking register access permissions. Change-Id: I3d06d0127cf165c1eeaf3302830742d610cef719 Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23766 Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/utility.cc | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'src/arch/arm/utility.cc') diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index d68850c5f..5ab56453b 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -289,6 +289,34 @@ getMPIDR(ArmSystem *arm_sys, ThreadContext *tc) } } +bool +HaveSecureEL2Ext(ThreadContext *tc) +{ + AA64PFR0 id_aa64pfr0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1); + return id_aa64pfr0.sel2; +} + +bool +IsSecureEL2Enabled(ThreadContext *tc) +{ + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); + if (ArmSystem::haveEL(tc, EL2) && HaveSecureEL2Ext(tc)) { + if (ArmSystem::haveEL(tc, EL3)) + return !ELIs32(tc, EL3) && scr.eel2; + else + return inSecureState(tc); + } + return false; +} + +bool +EL2Enabled(ThreadContext *tc) +{ + SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); + return ArmSystem::haveEL(tc, EL2) && + (!ArmSystem::haveEL(tc, EL3) || scr.ns || IsSecureEL2Enabled(tc)); +} + bool ELIs64(ThreadContext *tc, ExceptionLevel el) { -- cgit v1.2.3