From f48ad5b29d6f291b4f3679ff5fb7b5beae10d6fa Mon Sep 17 00:00:00 2001
From: Andreas Sandberg <andreas.sandberg@arm.com>
Date: Thu, 2 Jun 2016 13:38:30 +0100
Subject: arm: Correctly check FP/SIMD access permission in aarch32

The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1
and higher are all 32-bit. This breaks interprocessing since an
aarch64 EL1 uses different enable/disable bits. This change updates
the permission checks to according to what is prescribed by the ARM
ARM.

Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
---
 src/arch/arm/utility.cc | 85 -------------------------------------------------
 1 file changed, 85 deletions(-)

(limited to 'src/arch/arm/utility.cc')

diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index a4ae849c1..df00e8bcc 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -869,91 +869,6 @@ decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
     return (ok);
 }
 
-bool
-vfpNeonEnabled(uint32_t &seq, HCPTR hcptr, NSACR nsacr, CPACR cpacr, CPSR cpsr,
-               uint32_t &iss, bool &trap, ThreadContext *tc, FPEXC fpexc,
-               bool isSIMD)
-{
-    iss                     = 0;
-    trap                    = false;
-    bool undefined          = false;
-    bool haveSecurity       = ArmSystem::haveSecurity(tc);
-    bool haveVirtualization = ArmSystem::haveVirtualization(tc);
-    bool isSecure           = inSecureState(tc);
-
-    // Non-secure view of CPACR and HCPTR determines behavior
-    // Copy register values
-    uint8_t cpacr_cp10   = cpacr.cp10;
-    bool    cpacr_asedis = cpacr.asedis;
-    bool    hcptr_cp10   = false;
-    bool    hcptr_tase   = false;
-
-    bool cp10_enabled = cpacr.cp10 == 0x3
-                      || (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
-
-    bool cp11_enabled =  cpacr.cp11 == 0x3
-                      || (cpacr.cp11 == 0x1 && inPrivilegedMode(cpsr));
-
-    if (cp11_enabled) {
-        undefined |= !(fpexc.en && cp10_enabled);
-    } else {
-        undefined |= !(fpexc.en && cp10_enabled && (cpacr.cp11 == cpacr.cp10));
-    }
-
-    if (haveVirtualization) {
-        hcptr_cp10 = hcptr.tcp10;
-        undefined |= hcptr.tcp10 != hcptr.tcp11;
-        hcptr_tase = hcptr.tase;
-    }
-
-    if (haveSecurity) {
-        undefined |= nsacr.cp10 != nsacr.cp11;
-        if (!isSecure) {
-            // Modify register values to the Non-secure view
-            if (!nsacr.cp10) {
-                cpacr_cp10 = 0;
-                if (haveVirtualization) {
-                    hcptr_cp10 = true;
-                }
-            }
-            if (nsacr.nsasedis) {
-                cpacr_asedis = true;
-                if (haveVirtualization) {
-                    hcptr_tase = true;
-                }
-            }
-        }
-    }
-
-    // Check Coprocessor Access Control Register for permission to use CP10/11.
-    if (!haveVirtualization || (cpsr.mode != MODE_HYP)) {
-        switch (cpacr_cp10)
-        {
-            case 0:
-                undefined = true;
-                break;
-            case 1:
-                undefined |= inUserMode(cpsr);
-                break;
-        }
-
-        // Check if SIMD operations are disabled
-        if (isSIMD && cpacr_asedis) undefined = true;
-    }
-
-    // If required, check FPEXC enabled bit.
-    undefined |= !fpexc.en;
-
-    if (haveSecurity && haveVirtualization && !isSecure) {
-        if (hcptr_cp10 || (isSIMD && hcptr_tase)) {
-            iss  = isSIMD ? (1 << 5) : 0xA;
-            trap = true;
-        }
-    }
-
-    return (!undefined);
-}
-
 bool
 SPAlignmentCheckEnabled(ThreadContext* tc)
 {
-- 
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