From 0c4515ce1ff2a4e40d243df734af2a67cb8b1ad1 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2018 23:39:36 -0700 Subject: arch: Make the ISA register types aliases for the global types. The ISA specific types can thus be phased out. Change-Id: I8ea531a099fad140a4ec9c91cd972fe044111d60 Reviewed-on: https://gem5-review.googlesource.com/c/13623 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- src/arch/arm/registers.hh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/arch/arm') diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index 3c675cf77..3e0a74e69 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -59,11 +59,11 @@ const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + using ArmISAInst::MaxInstDestRegs; using ArmISAInst::MaxMiscDestRegs; -typedef uint64_t IntReg; +typedef RegVal IntReg; // floating point register file entry type -typedef uint64_t FloatRegBits; -typedef double FloatReg; +typedef RegVal FloatRegBits; +typedef FloatRegVal FloatReg; // Number of VecElem per Vector Register, computed based on the vector length constexpr unsigned NumVecElemPerVecReg = 4; @@ -73,7 +73,7 @@ using ConstVecReg = ::VecRegT; using VecRegContainer = VecReg::Container; // cop-0/cop-1 system control register -typedef uint64_t MiscReg; +typedef RegVal MiscReg; // condition code register; must be at least 32 bits for FpCondCodes typedef uint64_t CCReg; -- cgit v1.2.3