From 0cba96ba6a5d7a4dab2a63b14149c49dfbfbb3bc Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 26 May 2012 13:44:46 -0700 Subject: CPU: Merge the predecoder and decoder. These classes are always used together, and merging them will give the ISAs more flexibility in how they cache things and manage the process. --HG-- rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc --- src/arch/arm/SConscript | 5 +- src/arch/arm/decoder.cc | 88 +++++++++++++++++++++++++- src/arch/arm/decoder.hh | 103 +++++++++++++++++++++++++++++- src/arch/arm/predecoder.cc | 135 --------------------------------------- src/arch/arm/predecoder.hh | 154 --------------------------------------------- src/arch/arm/types.hh | 6 +- 6 files changed, 193 insertions(+), 298 deletions(-) delete mode 100644 src/arch/arm/predecoder.cc delete mode 100644 src/arch/arm/predecoder.hh (limited to 'src/arch/arm') diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 0f94455bd..44b6286a0 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -62,7 +62,6 @@ if env['TARGET_ISA'] == 'arm': Source('linux/system.cc') Source('miscregs.cc') Source('nativetrace.cc') - Source('predecoder.cc') Source('process.cc') Source('remote_gdb.cc') Source('stacktrace.cc') @@ -78,9 +77,9 @@ if env['TARGET_ISA'] == 'arm': SimObject('ArmTLB.py') DebugFlag('Arm') - DebugFlag('TLBVerbose') + DebugFlag('Decoder', "Instructions returned by the predecoder") DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") - DebugFlag('Predecoder', "Instructions returned by the predecoder") + DebugFlag('TLBVerbose') # Add in files generated by the ISA description. isa_desc_files = env.ISADesc('isa/main.isa') diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc index be46ff540..65badbc49 100644 --- a/src/arch/arm/decoder.cc +++ b/src/arch/arm/decoder.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 Google + * Copyright (c) 2012 Google * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -29,10 +29,96 @@ */ #include "arch/arm/decoder.hh" +#include "arch/arm/isa_traits.hh" +#include "arch/arm/utility.hh" +#include "base/trace.hh" +#include "cpu/thread_context.hh" +#include "debug/Decoder.hh" namespace ArmISA { DecodeCache Decoder::defaultCache; +void +Decoder::process() +{ + // emi is typically ready, with some caveats below... + instDone = true; + + if (!emi.thumb) { + emi.instBits = data; + emi.sevenAndFour = bits(data, 7) && bits(data, 4); + emi.isMisc = (bits(data, 24, 23) == 0x2 && + bits(data, 20) == 0); + consumeBytes(4); + DPRINTF(Decoder, "Arm inst: %#x.\n", (uint64_t)emi); + } else { + uint16_t word = (data >> (offset * 8)); + if (bigThumb) { + // A 32 bit thumb inst is half collected. + emi.instBits = emi.instBits | word; + bigThumb = false; + consumeBytes(2); + DPRINTF(Decoder, "Second half of 32 bit Thumb: %#x.\n", + emi.instBits); + } else { + uint16_t highBits = word & 0xF800; + if (highBits == 0xE800 || highBits == 0xF000 || + highBits == 0xF800) { + // The start of a 32 bit thumb inst. + emi.bigThumb = 1; + if (offset == 0) { + // We've got the whole thing. + emi.instBits = (data >> 16) | (data << 16); + DPRINTF(Decoder, "All of 32 bit Thumb: %#x.\n", + emi.instBits); + consumeBytes(4); + } else { + // We only have the first half word. + DPRINTF(Decoder, + "First half of 32 bit Thumb.\n"); + emi.instBits = (uint32_t)word << 16; + bigThumb = true; + consumeBytes(2); + // emi not ready yet. + instDone = false; + } + } else { + // A 16 bit thumb inst. + consumeBytes(2); + emi.instBits = word; + // Set the condition code field artificially. + emi.condCode = COND_UC; + DPRINTF(Decoder, "16 bit Thumb: %#x.\n", + emi.instBits); + if (bits(word, 15, 8) == 0xbf && + bits(word, 3, 0) != 0x0) { + foundIt = true; + itBits = bits(word, 7, 0); + DPRINTF(Decoder, + "IT detected, cond = %#x, mask = %#x\n", + itBits.cond, itBits.mask); + } + } + } + } +} + +//Use this to give data to the decoder. This should be used +//when there is control flow. +void +Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) +{ + data = inst; + offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC; + emi.thumb = pc.thumb(); + FPSCR fpscr = tc->readMiscReg(MISCREG_FPSCR); + emi.fpscrLen = fpscr.len; + emi.fpscrStride = fpscr.stride; + + outOfBytes = false; + process(); +} + } diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh index a91d70f48..dd51fd082 100644 --- a/src/arch/arm/decoder.hh +++ b/src/arch/arm/decoder.hh @@ -31,15 +31,95 @@ #ifndef __ARCH_ARM_DECODER_HH__ #define __ARCH_ARM_DECODER_HH__ -#include "arch/types.hh" +#include + +#include "arch/arm/miscregs.hh" +#include "arch/arm/types.hh" +#include "base/types.hh" #include "cpu/decode_cache.hh" -#include "cpu/static_inst_fwd.hh" + +class ThreadContext; namespace ArmISA { class Decoder { + protected: + ThreadContext * tc; + //The extended machine instruction being generated + ExtMachInst emi; + MachInst data; + bool bigThumb; + bool instDone; + bool outOfBytes; + int offset; + bool foundIt; + ITSTATE itBits; + + public: + void reset() + { + bigThumb = false; + offset = 0; + emi = 0; + instDone = false; + outOfBytes = true; + foundIt = false; + } + + Decoder(ThreadContext * _tc) : tc(_tc), data(0) + { + reset(); + } + + ThreadContext * getTC() + { + return tc; + } + + void + setTC(ThreadContext * _tc) + { + tc = _tc; + } + + void process(); + + //Use this to give data to the decoder. This should be used + //when there is control flow. + void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst); + + //Use this to give data to the decoder. This should be used + //when instructions are executed in order. + void moreBytes(MachInst machInst) + { + moreBytes(0, 0, machInst); + } + + inline void consumeBytes(int numBytes) + { + offset += numBytes; + assert(offset <= sizeof(MachInst)); + if (offset == sizeof(MachInst)) + outOfBytes = true; + } + + bool needMoreBytes() const + { + return outOfBytes; + } + + bool instReady() const + { + return instDone; + } + + int getInstSize() const + { + return (!emi.thumb || emi.bigThumb) ? 4 : 2; + } + protected: /// A cache of decoded instruction objects. static DecodeCache defaultCache; @@ -55,6 +135,25 @@ class Decoder { return defaultCache.decode(this, mach_inst, addr); } + + StaticInstPtr + decode(ArmISA::PCState &nextPC) + { + if (!instDone) + return NULL; + + assert(instDone); + ExtMachInst thisEmi = emi; + nextPC.npc(nextPC.pc() + getInstSize()); + if (foundIt) + nextPC.nextItstate(itBits); + thisEmi.itstate = nextPC.itstate(); + nextPC.size(getInstSize()); + emi = 0; + instDone = false; + foundIt = false; + return decode(thisEmi, nextPC.instAddr()); + } }; } // namespace ArmISA diff --git a/src/arch/arm/predecoder.cc b/src/arch/arm/predecoder.cc deleted file mode 100644 index a221f4e30..000000000 --- a/src/arch/arm/predecoder.cc +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2010 ARM Limited - * All rights reserved - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007-2008 The Florida State University - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "arch/arm/isa_traits.hh" -#include "arch/arm/predecoder.hh" -#include "arch/arm/utility.hh" -#include "base/trace.hh" -#include "cpu/thread_context.hh" -#include "debug/Predecoder.hh" - -namespace ArmISA -{ - -void -Predecoder::process() -{ - // emi is typically ready, with some caveats below... - emiReady = true; - - if (!emi.thumb) { - emi.instBits = data; - emi.sevenAndFour = bits(data, 7) && bits(data, 4); - emi.isMisc = (bits(data, 24, 23) == 0x2 && - bits(data, 20) == 0); - consumeBytes(4); - DPRINTF(Predecoder, "Arm inst: %#x.\n", (uint64_t)emi); - } else { - uint16_t word = (data >> (offset * 8)); - if (bigThumb) { - // A 32 bit thumb inst is half collected. - emi.instBits = emi.instBits | word; - bigThumb = false; - consumeBytes(2); - DPRINTF(Predecoder, "Second half of 32 bit Thumb: %#x.\n", - emi.instBits); - } else { - uint16_t highBits = word & 0xF800; - if (highBits == 0xE800 || highBits == 0xF000 || - highBits == 0xF800) { - // The start of a 32 bit thumb inst. - emi.bigThumb = 1; - if (offset == 0) { - // We've got the whole thing. - emi.instBits = (data >> 16) | (data << 16); - DPRINTF(Predecoder, "All of 32 bit Thumb: %#x.\n", - emi.instBits); - consumeBytes(4); - } else { - // We only have the first half word. - DPRINTF(Predecoder, - "First half of 32 bit Thumb.\n"); - emi.instBits = (uint32_t)word << 16; - bigThumb = true; - consumeBytes(2); - // emi not ready yet. - emiReady = false; - } - } else { - // A 16 bit thumb inst. - consumeBytes(2); - emi.instBits = word; - // Set the condition code field artificially. - emi.condCode = COND_UC; - DPRINTF(Predecoder, "16 bit Thumb: %#x.\n", - emi.instBits); - if (bits(word, 15, 8) == 0xbf && - bits(word, 3, 0) != 0x0) { - foundIt = true; - itBits = bits(word, 7, 0); - DPRINTF(Predecoder, - "IT detected, cond = %#x, mask = %#x\n", - itBits.cond, itBits.mask); - } - } - } - } -} - -//Use this to give data to the predecoder. This should be used -//when there is control flow. -void -Predecoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) -{ - data = inst; - offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC; - emi.thumb = pc.thumb(); - FPSCR fpscr = tc->readMiscReg(MISCREG_FPSCR); - emi.fpscrLen = fpscr.len; - emi.fpscrStride = fpscr.stride; - - outOfBytes = false; - process(); -} - -} diff --git a/src/arch/arm/predecoder.hh b/src/arch/arm/predecoder.hh deleted file mode 100644 index 87ba1777c..000000000 --- a/src/arch/arm/predecoder.hh +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2010 ARM Limited - * All rights reserved - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2007-2008 The Florida State University - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Stephen Hines - */ - -#ifndef __ARCH_ARM_PREDECODER_HH__ -#define __ARCH_ARM_PREDECODER_HH__ - -#include - -#include "arch/arm/miscregs.hh" -#include "arch/arm/types.hh" -#include "base/types.hh" - -class ThreadContext; - -namespace ArmISA -{ - class Predecoder - { - protected: - ThreadContext * tc; - //The extended machine instruction being generated - ExtMachInst emi; - MachInst data; - bool bigThumb; - bool emiReady; - bool outOfBytes; - int offset; - bool foundIt; - ITSTATE itBits; - - public: - void reset() - { - bigThumb = false; - offset = 0; - emi = 0; - emiReady = false; - outOfBytes = true; - foundIt = false; - } - - Predecoder(ThreadContext * _tc) : - tc(_tc), data(0) - { - reset(); - } - - ThreadContext * getTC() - { - return tc; - } - - void - setTC(ThreadContext * _tc) - { - tc = _tc; - } - - void process(); - - //Use this to give data to the predecoder. This should be used - //when there is control flow. - void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst); - - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(0, 0, machInst); - } - - inline void consumeBytes(int numBytes) - { - offset += numBytes; - assert(offset <= sizeof(MachInst)); - if (offset == sizeof(MachInst)) - outOfBytes = true; - } - - bool needMoreBytes() const - { - return outOfBytes; - } - - bool extMachInstReady() const - { - return emiReady; - } - - int getInstSize() const - { - return (!emi.thumb || emi.bigThumb) ? 4 : 2; - } - - //This returns a constant reference to the ExtMachInst to avoid a copy - ExtMachInst getExtMachInst(PCState &pc) - { - assert(emiReady); - ExtMachInst thisEmi = emi; - pc.npc(pc.pc() + getInstSize()); - if (foundIt) - pc.nextItstate(itBits); - thisEmi.itstate = pc.itstate(); - pc.size(getInstSize()); - emi = 0; - emiReady = false; - foundIt = false; - return thisEmi; - } - }; -} - -#endif // __ARCH_ARM_PREDECODER_HH__ diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 31dec7bcb..ebebbcc46 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -48,7 +48,7 @@ #include "base/hashmap.hh" #include "base/misc.hh" #include "base/types.hh" -#include "debug/Predecoder.hh" +#include "debug/Decoder.hh" namespace ArmISA { @@ -342,7 +342,7 @@ namespace ArmISA ITSTATE it = _itstate; uint8_t cond_mask = it.mask; uint8_t thumb_cond = it.cond; - DPRINTF(Predecoder, "Advancing ITSTATE from %#x,%#x.\n", + DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n", thumb_cond, cond_mask); cond_mask <<= 1; uint8_t new_bit = bits(cond_mask, 4); @@ -351,7 +351,7 @@ namespace ArmISA thumb_cond = 0; else replaceBits(thumb_cond, 0, new_bit); - DPRINTF(Predecoder, "Advancing ITSTATE to %#x,%#x.\n", + DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n", thumb_cond, cond_mask); it.mask = cond_mask; it.cond = thumb_cond; -- cgit v1.2.3